The Power Dissipation and Chip Area of Analog and Mixed-Signal Circuits Emerged Has As a Critical Design Constriction In Today's Vlsi Design Systems .This Paper Presents a Multilevel Design Optimization For Reducing the Power Dissipation and High Sampling Rates of a Pipelined Analog-To-Digital Converter. a 12 B 75-Msample/S Analog-To-Digital Converter Has Been Fabricated In A0.18-Um Cmos Technology. the Converter Uses Pipelined Seven Stages and Implements 2 Bit Per Stage Architecture. It Is a Fully Differential Analog Circuit With a Full-Scale Sinusoidal Input at 20 Mhz. It Dissipates 3.5M W.